Error correction and detection is one of the major problems to be solved when implementing a semi-conductor memory.
This problem is extensively addressed in the article "Error Correcting Codes for Semi-conductor Memory Applications: A State of the Art" by C. L. Chen and M. Y. Hsiao published in the IBM System Journal of Research and Development Volume 28, N 2 in Mar. 1984. This article is related to error correcting codes which are widely used for 1-bit error correction and 2-bit error detection and to block oriented error correction codes which may be used when the memory is organized in words comprising blocks of B-bits per block.
When each block comprises B=4 bits, twelve error correction bits need to be added to a 32-bit data word arranged in eight 4-bit blocks in order to be able to correct 1, 2, 3 or 4 bits in error in the same block and detect that two blocks are in error.
The aim of an error correction code is to improve the memory failure rate. There are two kinds of errors which may impair the failure rate, namely the permanent hard errors which have a low probability of occurrence but impairs the memory failure rate since they may affect several bits at one and the same time and the temporary soft errors which have a higher probability of occurrence but only affect one bit at one and the same time. The major contributors to the memory failure rate are the hard errors, the soft errors aligned with hard errors and the soft errors. Almost all known error correction codes are able to protect the memory against the two first error causes, this means that they are able to correct all errors in one module and,detect several errors in two different modules.
The error correction codes known as single bit error correction/double bit error detection SEC/DED as described in above referenced article, allow a good failure rate to be obtained for a 32-bit word using 7 or 8 ECC bits when the memory is organized in 1-bit block.
The single block correction/double block detection code SBC/DBD, needs 12 ECC bits when a 32-bit memory word is organized in eight 4-bit blocks to reach the same failure rate. Generally, the memory comprises several modules and the different blocks of words are located in the different modules. Low cost memories comprised of 10 modules exist. But they cannot be used in environments where the memory reliability is a key factor.